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1 for more information www.linear.com/LTC6948 typical a pplica t ion fea t ures descrip t ion ultralow noise 0.37ghz to 6.39ghz fractional-n synthesizer with integrated vco the lt c ? 6948 is a high performance, low noise, 6.39ghz phase-locked loop (pll) with a fully integrated vco, including a reference divider, phase-frequency detector (pfd), ultralow noise charge pump, fractional feedback divider, and vco output divider. the fractional divider uses an advanced, 4th order ? modulator which provides exceptionally low spurious levels. this allows wide loop bandwidths, producing extremely low integrated phase noise values. the programmable vco output divider, with a range of 1 through 6, extends the output frequency range. output frequency options LTC6948-1 LTC6948-2 LTC6948-3 LTC6948-4 o_div = 1 2.240 to 3.740 3.080 to 4.910 3.840 to 5.790 4.200 to 6.390 o_div = 2 1.120 to 1.870 1.540 to 2.455 1.920 to 2.895 2.100 to 3.195 o_div = 3 0.747 to 1.247 1.027 to 1.637 1.280 to 1.930 1.400 to 2.130 o_div = 4 0.560 to 0.935 0.770 to 1.228 0.960 to 1.448 1.050 to 1.598 o_div = 5 0.448 to 0.748 0.616 to 0.982 0.768 to 1.158 0.840 to 1.278 o_div = 6 0.373 to 0.623 0.513 to 0.818 0.640 to 0.965 0.700 to 1.065 6.3ghz wideband receiver a pplica t ions n low noise fractional-n pll with integrated vco n no ?- modulator spurs n 18-bit fractional denominator n C226 dbc/hz normalized in-band phase noise floor n C274 dbc/hz normalized in-band 1/f noise n C157 dbc/hz wideband output phase noise floor n excellent integer boundary spurious performance n output divider (1 to 6, 50% duty cycle) n output buffer muting n reference input frequency up to 425mhz n fast frequency switching n fracnwizard? software design tool support n wireless basestations (lte, wimax, w-cdma, pcs) n microwave data links n military and secure radio n test and measurement l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks and fracnwizard is a trademark of analog devices, inc. all other trademarks are the property of their respective owners. unused output available for other use 50 0.1f r = 2, f pfd = 50mhz n = 84 to 127.8 lbw = 186khz o = 1 0.01f 1f 0.01f 5v 3.3v 0.1f 68nh 68nh 0.01f 3.3v 76.8 100pf 100pf 1.6nf 3.3v f lo = 4200mhz to 6390mhz in 190.7hz steps LTC6948-4 stat tune cs mute sdi v d + ldo rf + rf ? gnd sclk tb gnd v rf + ref + bb sdo cm c cm b cm a gnd bvco v vco + gnd v cp + cp v ref + ref ? gnd 0.1f 100mhz 51.1 1f 3.3v 1f 0.1f 3.3v 1f 2.2f 15 1f 6948 ta01a spi bus 10h rf input signal if output if lo rf 76.8 56nf 2.4nf LTC6948-4 phase noise, f rf = 6236mhz offset frequency (hz) ?140 phase noise (dbc/hz) ?130 ?110 ?90 100 10k 100k 10m 40m 6946 ta01b ?150 1k 1m ?100 ?120 ?160 rms noise = 0.412 rms jitter = 183fs f pfd = 50mhz loop bw = 186khz intn = 0 cple = 1 lt c6948 6948fa
2 for more information www.linear.com/LTC6948 p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltages v + (v ref + , v rf + , v d + ) to gnd ............................... 3. 6v v cp + , v vco + to gnd ............................................. 5 .5v voltage on cp pin ................. gn d C 0.3v to v cp + + 0.3v voltage on all other pins ........... gn d C 0.3v to v + + 0.3v operating junction temperature range, t j (note 2) lt c6 948 i ........................................... C 40 c to 105 c junction temperature, t jmax ................................ 125 c storage temperature range .................. C 65 c to 150 c (note 1) 9 10 top view 29 gnd ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 27 26 25 24 14 23 6 5 4 3 2 1 ref + stat cs sclk sdi sdo ldo v d + bvco gnd cm a cm b cm c gnd tb tune ref ? v ref + cp v cp + gnd v vco + mute gnd rf ? rf + v rf + bb 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, jcbottom = 7c/w exposed pad (pin 29) is gnd, must be soldered to pcb o r d er i n f or m a t ion a vailable o p t ions lead free finish tape and reel part marking package description junction temperature range LTC6948iufd-1#pbf LTC6948iufd-1#trpbf 69481 28-lead (4mm 5mm) plastic qfn C40c to 105c LTC6948iufd-2#pbf LTC6948iufd-2#trpbf 69482 28-lead (4mm 5mm) plastic qfn C40c to 105c LTC6948iufd-3#pbf LTC6948iufd-3#trpbf 69483 28-lead (4mm 5mm) plastic qfn C40c to 105c LTC6948iufd-4#pbf LTC6948iufd-4#trpbf 69484 28-lead (4mm 5mm) plastic qfn C40c to 105c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to : http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ vco frequency range (ghz) package style output frequency range vs output divider setting (ghz) qfn-28 (ufd28) 0 div = 6 0 div = 5 0 div = 4 0 div = 3 0 div = 2 0 div = 1 2.240 to 3.740 LTC6948iufd-1 0.373 to 0.623 0.448 to 0.748 0.560 to 0.935 0.747 to 1.247 1.120 to 1.870 2.240 to 3.740 3.080 to 4.910 LTC6948iufd-2 0.513 to 0.818 0.616 to 0.982 0.770 to 1.228 1.027 to 1.637 1.540 to 2.455 3.080 to 4.910 3.840 to 5.790 LTC6948iufd-3 0.640 to 0.965 0.768 to 1.158 0.960 to 1.448 1.280 to 1.930 1.920 to 2.895 3.840 to 5.790 4.200 to 6.390 LTC6948iufd-4 0.700 to 1.065 0.840 to 1.278 1.050 to 1.598 1.400 to 2.130 2.100 to 3.195 4.200 to 6.390 overlapping frequency bands http://www.linear.com/product/LTC6948#orderinfo lt c6948 6948fa
3 for more information www.linear.com/LTC6948 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units reference inputs (ref + , ref C ) f ref input frequency l 10 425 mhz v ref input signal level single-ended, 1f ac-coupling capacitors l 0.5 2 2.7 v p-p input slew rate l 20 v/s input duty cycle 50 % self-bias voltage l 1.65 1.85 2.25 v input resistance differential l 5.8 8.4 11.6 k input capacitance differential 14 pf vco f vco frequency range LTC6948-1 (note 3) LTC6948-2 (note 3) LTC6948-3 (note 3) LTC6948-4 (note 3) l l l l 2.24 3.08 3.84 4.20 3.74 4.91 5.79 6.39 ghz ghz ghz ghz k vco tuning sensitivity LTC6948-1 (notes 3, 4) LTC6948-2 (notes 3, 4) LTC6948-3 (notes 3, 4) LTC6948-4 (notes 3, 4) l l l l 4.7 to 7.2 4.7 to 7.0 4.0 to 6.0 4.5 to 6.5 %hz/v %hz/v %hz/v %hz/v rf output (rf + , rf C ) f rf output frequency l 0.373 6.39 ghz o output divider range all integers included l 1 6 output duty cycle 50 % output resistance single-ended, each output to v rf + l 100 136 175 p rf-se output power, single-ended, f rf = 900mhz rfo[1:0] = 0, r z = 50, lc match rfo[1:0] = 1, r z = 50, lc match rfo[1:0] = 2, r z = 50, lc match rfo[1:0] = 3, r z = 50, lc match l l l l C9 C6.1 C2.9 0.1 C 7.3 C4.5 C1.4 1.5 C5.5 C2.8 0.2 3 dbm dbm dbm dbm output power, muted, f rf = 900mhz r z = 50, single-ended, o = 2 to 6 l C80 dbm mute enable time l 110 ns mute disable time l 170 ns phase/frequency detector f pfd input frequency integer mode fractional mode ldoen = 0 ldov = 3, ldoen = 1 ldov = 2, ldoen = 1 ldov = 1, ldoen = 1 ldov = 0, ldoen = 1 l l l l l l 100 76.1 66.3 56.1 45.9 34.3 mhz mhz mhz mhz mhz mhz charge pump i cp output current range 8 settings (see table 6) 1 11.2 ma output current source/sink accuracy all settings, v(cp) = v cp + /2 6 % output current source/sink matching i cp = 1.0ma to 2.8ma, v(cp) = v cp + /2 i cp = 4.0ma to 11.2ma, v(cp) = v cp + /2 3.5 2 % % output current vs output voltage sensitivity (note 5) l 0.2 1 %/v output current vs temperature v(cp) = v cp + /2 l 170 ppm/c output hi-z leakage current i cp = 11.2ma, cpclo = cpchi = 0 (note 5) 0.03 na the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v unless otherwise specified (note 2). all voltages are with respect to gnd. lt c6948 6948fa
4 for more information www.linear.com/LTC6948 e lec t rical c harac t eris t ics symbol parameter conditions min typ max units v clmp-lo low clamp voltage cpclo = 1 0.84 v v clmp-hi high clamp voltage cpchi = 1, referred to v cp + C0.96 v v mid mid-supply output bias ratio referred to (v cp + C gnd) 0.48 v/v reference (r) divider r divide range all integers included l 1 31 counts vco (n) divider n divide range all integers included, integer mode all integers included, fractional mode l l 32 35 1023 1019 counts counts fractional ? modulator numerator range all integers included l 1 262143 counts modulator ldo output voltage ldo enabled, four values ldo disabled 1.7 to 2.6 v d + v v external pin capacitance required for ldo stability l 0.047 0.1 1 f digital pin specifications v ih high level input voltage mute, cs, sdi, sclk l 1.55 v v il low level input voltage mute, cs, sdi, sclk l 0.8 v v ihys input voltage hysteresis mute, cs, sdi, sclk 250 mv input current mute, cs, sdi, sclk l 1 a i oh high level output current sdo and stat, v oh = v d + C 400mv l C3.3 C1.9 ma i ol low level output current sdo and stat, v ol = 400mv l 2.0 3.4 ma sdo hi-z current l 1 a digital timing specifications (see figure 6 and figure 7) t ckh sclk high time l 25 ns t ckl sclk low time l 25 ns t css cs setup time l 10 ns t csh cs high time l 10 ns t cs sdi to sclk setup time l 6 ns t ch sdi to sclk hold time l 6 ns t do sclk to sdo time to v ih /v il /hi-z with 30pf load l 16 ns power supply voltages v ref + supply range l 3.15 3.3 3.45 v v d + supply range l 3.15 3.3 3.45 v v rf + supply range l 3.15 3.3 3.45 v v vco + supply range l 4.75 5.0 5.25 v v cp + supply range l 4.0 5.25 v power supply currents i dd v d + supply current digital inputs at supply levels, integer mode digital inputs at supply levels, fractional mode, f pfd = 66.3mhz, ldov[1:0] = 3 l l 18.2 1500 22 a ma i cc(5v) sum v cp + , v vco + supply currents i cp = 11.2ma i cp = 1.0ma pdall = 1 l l l 48 26 450 60 35 1000 ma ma a the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v unless otherwise specified (note 2). all voltages are with respect to gnd. lt c6948 6948fa
5 for more information www.linear.com/LTC6948 e lec t rical c harac t eris t ics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC6948i is guaranteed to meet specified performance limits over the full operating junction temperature range of C40c to 105c. symbol parameter conditions min typ max units i cc(3.3v) sum v ref + , v rf + supply currents rf muted, od[2:0] = 1 rf enabled, rfo[1:0] = 0, od[2:0] = 1 rf enabled, rfo[1:0] = 3, od[2:0] = 1 rf enabled, rfo[1:0] = 3, od[2:0] = 2 rf enabled, rfo[1:0] = 3, od[2:0] = 3 rf enabled, rfo[1:0] = 3, od[2:0] = 4 to 6 pdall = 1 l l l l l l l 70.4 81.1 91.3 109.2 114.8 119.6 53 80 95 105 125 135 140 250 ma ma ma ma ma ma a phase noise and spurious l vco vco phase noise (LTC6948-1, f vco = 3.0ghz, f rf = 3.0ghz, od [2:0] = 1 (note 6)) 10khz offset 1mhz offset 40mhz offset C 80 C130 C157 dbc/hz dbc/hz dbc/hz vco phase noise (LTC6948 -2, f vco = 4.0ghz, f rf = 4.0ghz, od [2:0] = 1 (note 6)) 10khz offset 1mhz offset 40mhz offset C 77 C127 C156 dbc/hz dbc/hz dbc/hz vco phase noise (LTC6948 -3, f vco = 5.0ghz, f rf = 5.0ghz, od [2:0] = 1 (note 6)) 10khz offset 1mhz offset 40mhz offset C 75 C126 C155 dbc/hz dbc/hz dbc/hz vco phase noise (LTC6948 -4, f vco = 6.0ghz, f rf = 6.0ghz, od [2:0] = 1 (note 6)) 10khz offset 1mhz offset 40mhz offset C 73 C123 C154 dbc/hz dbc/hz dbc/hz vco phase noise (LTC6948 -3, f vco = 5.0ghz, f rf = 2.50ghz, od[ 2? :0] = 2 (note 6)) 10khz offset 1mhz offset 40mhz offset C 81 C132 C155 dbc/hz dbc/hz dbc/hz vco phase noise (LTC6948 -3, f vco = 5.0ghz, f rf = 1.667ghz, od[ 2? :0] = 3 (note 6)) 10khz offset 1mhz offset 40mhz offset C 84 C135 C156 dbc/hz dbc/hz dbc/hz vco phase noise (LTC6948 -3, f vco = 5.0ghz, f rf = 1.25ghz, od[ 2? :0] = 4 (note 6)) 10khz offset 1mhz offset 40mhz offset C 87 C138 C156 dbc/hz dbc/hz dbc/hz vco phase noise (LTC6948 -3, f vco = 5.0ghz, f rf = 1.00ghz, od[ 2? :0] = 5 (note 6)) 10khz offset 1mhz offset 40mhz offset C 89 C140 C157 dbc/hz dbc/hz dbc/hz vco phase noise (LTC6948 -3, f vco = 5.0ghz, f rf = 0.833ghz, od[ 2? :0] = 6 (note 6)) 10khz offset 1mhz offset 40mhz offset C 90 C141 C158 dbc/hz dbc/hz dbc/hz l norm(int) integer normalized in-band phase noise floor intn = 1, i cp = 5.6ma (notes 7, 8, 10) C226 dbc/hz l norm(frac) fractional normalized in-band phase noise floor intn = 0, cple = 1, i cp = 5.6ma (notes 7, 8, 10) C 225 dbc/hz l 1 /f normalized in-band 1/f phase noise i cp = 11.2ma (notes 7, 11) C274 dbc/hz in-band phase noise floor fractional mode, cple = 1 (notes 7, 9, 10, 12) C 113 dbc/hz integrated phase noise from 100hz to 40mhz fractional mode, cple = 1 (notes 9, 12) 0.14 rms spurious fractional mode, f offset = f pfd , pll locked (notes 8, 13, 14) C 98 dbc the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v ref + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v unless otherwise specified (note 2). all voltages are with respect to gnd. lt c6948 6948fa
6 for more information www.linear.com/LTC6948 t a = 25 c . v ref + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v, intn = 0, dithen = 1, cple = 1, rfo [1:0] = 3, unless otherwise noted. typical p er f or m ance c harac t eris t ics e lec t rical c harac t eris t ics note 3: valid for 1.60v v(tune) 2.85v with part calibrated after a power cycle or software power-on reset (por). note 4: based on characterization. note 5: for 0.9v < v(cp) < (v cp + C 0.9v). note 6: measured outside the loop bandwidth, using a narrowband loop, rfo[1:0] = 3. note 7: measured inside the loop bandwidth with the loop locked. note 8: reference frequency supplied by wenzel 501-04516, f ref = 100mhz, p ref = 10dbm. note 9: reference frequency supplied by wenzel 500-23571, f ref = 61.44mhz, p ref = 10dbm. note 10: output phase noise floor is calculated from normalized phase noise floor by l out = l norm + 10log 10 (f pfd ) + 20log 10 (f rf /f pfd ). note 11: output 1/f noise is calculated from normalized 1/f phase noise by l out(1/f) = l 1/f + 20log 10 (f rf ) C 10log10 (f offset ). note 12: i cp = 5.6ma, f pfd = 61.44mhz, filt[1:0] = 0, loop?bw?=?180khz; f rf = 2377.7mhz, f vco = 4755.4mhz (LTC6948-3) note 13: i cp = 5.6ma, f pfd = 25mhz, filt[1:0] = 0, loop?bw?=?73khz; f rf = 891.85mhz, f vco = 2675hz (LTC6948-1), f vco = 4459mhz (LTC6948 - 2), f vco = 5351mhz (LTC6948-3, LTC6948-4). note 14: measured using dc1959. charge pump sink current error vs voltage, output current ref input sensitivity vs frequency charge pump sink current error vs voltage, temperature cp hi-z current vs voltage, temperature charge pump source current error vs voltage, output current tune current vs voltage, temperature frequency (mhz) 0 sensitivity (dbm) ?15 ?20 ?25 ?30 ?35 ?40 ?45 ?50 400 6948 g01 100 200 300 450 350 50 150 250 bst = 1 filt = 0 105c 25c ?40c output voltage (v) 0 current (na) 5 4 3 2 1 0 ?1 ?2 ?3 ?5 ?4 4.0 6948 g02 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 i cp = 11.2ma cprst = 1 cple = 0 105c 25c ?40c voltage (v) 0 current (na) 5 4 3 2 1 0 ?1 ?2 ?3 ?5 ?4 6948 g03 1.0 2.0 3.0 0.5 1.5 2.5 105c 25c ?40c output voltage (v) 0 error (%) 5 4 3 2 1 0 ?1 ?2 ?3 ?5 ?4 4.0 6948 g04 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 cple = 0 1ma 5.6ma 11.2ma output voltage (v) 0 error (%) 5 4 3 2 1 0 ?1 ?2 ?3 ?5 ?4 4.0 6948 g05 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 i cp = 11.2ma cple = 0 105c 25c ?40c output voltage (v) 0 error (%) 5 4 3 2 1 0 ?1 ?2 ?3 ?5 ?4 4.0 6948 g06 1.0 2.0 3.0 5.0 3.5 0.5 1.5 2.5 4.5 cple = 0 1ma 5.6ma 11.2ma lt c6948 6948fa
7 for more information www.linear.com/LTC6948 t a = 25 c . v ref + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v, intn = 0, dithen = 1, cple = 1, rfo [1:0] = 3, unless otherwise noted. typical p er f or m ance c harac t eris t ics rf output hd3 vs output divide (single-ended on rf + ) charge pump source current error vs voltage, temperature mute output power vs f vco and output divide (single-ended on rf + ) rf output power vs frequency (single-ended on rf + ) LTC6948-3 frequency step transient rf output hd2 vs output divide (single-ended on rf + ) LTC6948 -1 vco tuning sensitivity LTC6948 -2 vco tuning sensitivity LTC6948 -3 vco tuning sensitivity output voltage (v) 0 error (%) 1 3 5 4.0 6948 g07 ?1 ?3 0 2 4 ?2 ?4 ?5 1.00.5 2.01.5 3.0 3.5 4.5 2.5 5.0 105c 25c ?40c i cp = 11.2ma cple = 0 frequency (ghz) 0.5 p out (dbm) ?2.5 0.5 1.0 2.0 1.5 1.5 3.5 4.5 6948 g08 ?0.5 ?1.5 ?3.0 0 ?3.5 ?1.0 ?2.0 2.5 5.5 6.5 105c 25c ?40c LTC6948-4 l c = 68nh c s = 100pf f vco (ghz) 4.2 ?55 ?50 hd2 (dbc) ?45 ?40 ?35 ?30 5.0 5.8 6.6 6948 g09 ?25 ?20 4.6 5.4 6.2 LTC6948-4, l c = 68nh, c s = 100pf , f rf = f vco /o o = 3 o = 2 o = 1 o = 6 o = 4 o = 5 4.2 5.0 5.8 6.6 4.6 5.4 6.2 f vco (ghz) ?45 ?40 hd3 (dbc) ?35 ?30 ?25 ?20 6948 g10 ?15 ?10 ?5 LTC6948-4 l c = 68nh c s = 100pf f rf = f vco /o o = 6 o = 3 o = 2 o = 1 o = 5 o = 4 4.2 5.0 5.8 6.6 4.6 5.4 6.2 f vco (mhz) p out at f vco /o (dbm) ?75 ?65 ?55 6948 g11 ?85 ?95 ?45 LTC6948-4, l c = 68nh c s = 100pf, f rf = f vco /o o = 1 o = 4 o = 6 o = 5 o = 2 o = 3 time (s) ?5 0 2.2 frequency (ghz) 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3.0 5 10 15 20 6948 g12 25 calibration time 126mhz step f pfd = 61.44mhz f cal = 1.28mhz loop bw = 180khz mtcal = 0 o = 2 frequency (ghz) 2.2 2.4 2.6 2.8 3.0 k vco (%/v) 3.5 4.5 5.0 5.5 8.0 6.5 6948 g13 4.0 7.0 7.5 6.0 3.8 3.63.43.23.0 frequency (ghz) 3.0 3.2 3.4 3.6 3.8 3.0 k vco (%/v) 3.5 4.5 5.0 5.5 8.0 6.5 6948 g14 4.0 7.0 7.5 6.0 5.0 4.84.64.44.24.0 frequency (ghz) 3.8 2.5 k vco (%/v) 3.0 4.0 4.5 5.0 5.0 7.0 6948 g15 3.5 4.2 5.4 4.6 5.8 5.5 6.0 6.5 lt c6948 6948fa
8 for more information www.linear.com/LTC6948 t a = 25 c . v ref + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v, intn = 0, dithen = 1, cple = 1, rfo [1:0] = 3, unless otherwise noted. typical p er f or m ance c harac t eris t ics LTC6948-1 vco phase noise LTC6948-2 vco phase noise LTC6948-3 vco phase noise LTC6948-4 vco phase noise LTC6948-1 vco phase noise vs f vco , output divide (f offset = 10khz) LTC6948-2 vco phase noise vs f vco , output divide (f offset = 10khz) LTC6948 -4 vco tuning sensitivity normalized in-band phase noise floor vs f vco normalized in-band phase noise floor vs cp current frequency (ghz) 4.3 4.7 5.1 3.0 k vco (%/v) 3.5 4.5 5.0 5.5 7.5 6.5 6948 g16 4.0 7.0 6.0 6.7 6.35.95.5 offset frequency (hz) 1k ?100 phase noise (dbc/hz) ?90 ?80 ?70 ?60 100k 10k 1m 10m 40m 6948 g19 ?110 ?130 ?150 ?120 ?140 ?160 ?50 ?40 f rf = f vco = 3ghz offset frequency (hz) 1k ?100 phase noise (dbc/hz) ?90 ?80 ?70 ?60 100k 10k 1m 10m 40m 6948 g22 ?110 ?130 ?150 ?120 ?140 ?160 ?50 ?40 f rf = f vco = 6ghz f vco (ghz) 2.2 ?105 phase noise (dbc/hz) ?100 ?95 ?90 ?85 ?75 2.4 2.6 2.8 3.0 6948 g23 3.2 3.4 3.6 3.8 ?80 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 5 o = 4 ?100 ?95 ?90 ?85 ?80 ?70 ?75 f vco (ghz) 3.0 phase noise (dbc/hz) 3.3 3.6 3.9 6948 g24 4.2 4.5 4.8 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 4 o = 5 offset frequency (hz) 1k ?100 phase noise (dbc/hz) ?90 ?80 ?70 ?60 100k 10k 1m 10m 40m 6948 g20 ?110 ?130 ?150 ?120 ?140 ?160 ?50 ?40 f rf = f vco = 4ghz offset frequency (hz) 1k ?100 phase noise (dbc/hz) ?90 ?80 ?70 ?60 100k 10k 1m 10m 40m 6948 g21 ?110 ?130 ?150 ?120 ?140 ?160 ?50 ?40 f rf = f vco = 5ghz f vco (ghz) 2 ?227 phase noise floor (dbc/hz) ?226 ?224 3 6948 g17 4 ?222 ?225 ?223 5 6 i cp = 5.6ma cple = 1 fractional-n integer-n i cp (ma) 1 ?227 phase noise floor (dbc/hz) ?226 3 5 6948 g18 7 ?224 ?222 ?225 ?223 9 11 f vco = 5ghz cple = 1 fractional-n integer-n lt c6948 6948fa
9 for more information www.linear.com/LTC6948 t a = 25 c . v ref + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v, intn = 0, dithen = 1, cple = 1, rfo [1:0] = 3, unless otherwise noted. typical p er f or m ance c harac t eris t ics LTC6948-2 vco phase noise vs f vco , output divide (f offset = 1mhz) LTC6948-3 vco phase noise vs f vco , output divide (f offset = 1mhz) LTC6948-4 vco phase noise vs f vco , output divide (f offset = 1mhz) closed-loop phase noise, LTC6948-1 f rf = 891.857mhz closed-loop phase noise, LTC6948-3 f rf = 2377.728mhz closed-loop phase noise, LTC6948-2 f rf = 3646.464mhz LTC6948-3 vco phase noise vs f vco , output divide (f offset = 10khz) LTC6948-4 vco phase noise vs f vco , output divide (f offset = 10khz) LTC6948-1 vco phase noise vs f vco , output divide (f offset = 1mhz) ?150 ?145 ?140 ?135 ?125 ?130 f vco (ghz) 2.2 phase noise (dbc/hz) 2.4 2.6 2.8 3.0 6948 g27 3.2 3.4 3.6 3.8 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 4 o = 5 ?80 ?75 ?70 ?85 ?90 ?95 f vco (ghz) 3.8 phase noise (dbc/hz) 4.2 6948 g25 4.6 5.0 5.4 5.8 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 4 o = 5 ?130 ?125 ?135 ?140 ?145 f vco (ghz) 3.0 phase noise (dbc/hz) 3.3 3.6 3.9 6948 g28 4.2 4.5 4.8 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 4 o = 5 ?130 ?125 ?120 ?135 ?140 ?145 f vco (ghz) 3.8 phase noise (dbc/hz) 4.2 6948 g29 4.6 5.0 5.4 5.8 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 4 o = 5 4.3 4.7 5.1 5.5 5.9 6.7 6.3 ?130 ?125 ?120 ?135 ?140 ?145 f vco (ghz) phase noise (dbc/hz) 6948 g30 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 4 o = 5 ?80 ?75 ?70 ?85 ?90 ?95 f vco (ghz) 4.3 phase noise (dbc/hz) 4.7 6948 g26 5.1 5.5 5.9 6.7 6.3 f rf = f vco /o o = 1 o = 2 o = 3 o = 6 o = 4 o = 5 offset frequency (hz) ?140 phase noise (dbc/hz) ?130 ?110 ?90 100 10k 100k 10m 40m 6948 g31 ?150 1k 1m ?100 ?120 ?160 rms noise = 0.074 f pfd = 25mhz o = 3 intn = 0 cple = 1 f ib-spur = 572khz loop bw = 73khz notes 8, 13 offset frequency (hz) ?140 phase noise (dbc/hz) ?130 ?110 ?90 100 10k 100k 10m 40m 6948 g32 ?150 1k 1m ?100 ?120 ?160 rms noise = 0.141 f pfd = 61.44mhz o = 2 intn = 0 cple = 1 loop bw = 180khz notes 9, 12 offset frequency (hz) ?140 phase noise (dbc/hz) ?130 ?110 ?90 100 10k 100k 10m 40m 6948 g33 ?150 1k 1m ?100 ?120 ?160 rms noise = 0.224 f pfd = 61.44mhz o = 1 intn = 0 cple = 1 loop bw = 178khz note 9 lt c6948 6948fa
10 for more information www.linear.com/LTC6948 t a = 25 c . v ref + = v d + = v rf + = 3.3v, v cp + = v vco + = 5v, intn = 0, dithen = 1, cple = 1, rfo [1:0] = 3, unless otherwise noted. typical p er f or m ance c harac t eris t ics integer boundary spur power vs output frequency, LTC6948-3 LTC6948-4 supply current v d + supply current vs ldov, f pfd (intn = 0, pdfn = 0) v d + supply current vs ldov, temperature (intn = 0, pdfn = 0, f pfd noted) LTC6948-1 spurious response f rf = 891.85mhz, f ref = 100mhz, f pfd = 25mhz, loop bw = 74khz LTC6948-3 spurious response f rf = 2377.73mhz, f ref = 61.44mhz, f pfd = 61.44mhz, loop bw = 180k LTC6948-4 spurious response f rf = 6236mhz, f ref = 100mhz, f pfd = 50mhz, loop bw = 152khz frequency offset (mhz in 10khz segments) ?100 ?100dbc ?75 ?140 p out (dbm) ?120 ?100 ?80 25 50 75 0 6948 g34 ?50 ?25 0 100 ?60 ?40 ?20 rbw = 10hz vbw = 10hz intn = 0 cple = 1 o = 3 notes 8, 14 ?103dbc output frequency (ghz) 0 ?80 ib spur level (dbc) ?75 ?70 ?65 ?60 ?40 0.5 1.5 2.5 6948 g37 3.5 4.5 1 2 3 4 5 5.5 ?55 ?50 ?45 o = 1 o = 2 o = 3 o = 6 o = 5 o = 4 spur in band f pfd = 50mhz cple = 1 f pfd (mhz) 5 15 0 2 4 6 8 supply current (ma) 10 12 14 16 20 25 35 45 55 6948 g39 65 75 18 ldoen = 0 ldov = 3 ldov = 2 ldov = 1 ldov = 0 tc = 25c t j (c) ?40 83 3.3v current (ma) 5v current (ma) 84 86 ?20 0 20 40 6948 g38 60 88 92 91 90 85 87 89 30 32 34 36 39 38 37 31 33 35 80 100 o = 1, mute = 0 rfo = 3, i cp = 5.6ma excludes v d + t j (c) ?40 ?20 4 6 8 supply current (ma) 10 12 14 16 20 0 20 40 60 6948 g40 80 100 18 ldoen = 0, 75mhz ldov = 3, 65mhz ldov = 2, 55mhz ldov = 1, 45mhz ldov = 0, 30mhz frequency offset (mhz in 10khz segments) ?246 ?96dbc ?78dbc ?78dbc ?184 ?140 p out (dbm) ?120 ?100 ?80 61.4 123 184 0 6948 g35 ?123?61.4 0 246 ?60 ?40 ?20 rbw = 100hz vbw = 100hz intn = 0 cple = 1 o = 2 notes 9, 14 ?91dbc frequency offset (mhz in 10khz segments) ?200 ?70dbc ?150 ?140 p out (dbm) ?120 ?100 ?80 50 100 150 0 6948 g36 ?100 ?50 0 200 ?60 ?40 ?20 rbw = 100hz vbw = 100hz intn = 0 cple = 1 o = 1 notes 8, 14 ?72dbc lt c6948 6948fa
11 for more information www.linear.com/LTC6948 p in func t ions ref + , ref C (pins 1, 28): reference input signals. this differential input is buffered with a low noise amplifier, which feeds the reference divider. they are self-biased and must be ac-coupled with 1f capacitors. if used single- ended with v ref + 2.7v p-p , bypass ref C to gnd with a 1f capacitor. if used single-ended with v ref + > 2.7v p-p , bypass ref C to gnd with a 47pf capacitor. stat (pin 2) : status output. this signal is a configurable logical or combination of the unlok, lok, alchi, alclo, thi, and tlo status bits, programmable via the status register. see the operation section for more details. cs (pin 3): serial port chip select. this cmos input initi - ates a serial port communication burst when driven low, ending the burst when driven back high. see the operation section for more details. sclk (pin 4): serial port clock. this cmos input clocks serial port input data on its rising edge. see the operation section for more details. sdi (pin 5) : serial port data input. the serial port uses this cmos input for data. see the operation section for more details. sdo (pin 6): serial port data output. this cmos three- state output presents data from the serial port during a read communication burst. optionally attach a resistor of >200k to gnd to prevent a floating output. see the ap - plications information section for more details. ldo (pin 7) : ? modulator ldo bypass pin. this pin should be bypassed directly to the ground plane using a low esr ( <0.8) 0.1f ceramic capacitor as close to the pin as possible. v d + (pin 8): 3.15v to 3.45v positive supply pin for serial port and ? modulator circuitry. this pin should be by- passed directly to the ground plane using a 0.1f ceramic capacitor as close to the pin as possible. mute (pin 9) : rf mute. the cmos active-low input mutes the rf differential outputs while maintaining internal bias levels for quick response to deassertion. gnd (pins 10, 17, 21, exposed pad pin 29): negative power supply (ground). these pins should be tied directly to the ground plane with multiple vias for each pin. the package exposed pad must be soldered directly to the pcb land. the pcb land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance. rf C , rf + (pins 11, 12): rf output signals. the vco output divider is buffered and presented differentially on these pins. the outputs are open-collector, with 136 (typical) pull-up resistors tied to v rf + to aid impedance matching. if used single-ended, the unused output should be terminated to 50. see the applications information section for more details on impedance matching. v rf + (pin 13): 3.15v to 3.45v positive supply pin for rf circuitry. this pin should be bypassed directly to the ground plane using a 0.01f ceramic capacitor as close to the pin as possible. bb (pin 14): rf reference bypass. this output has a 2.5k resistance and must be bypassed with a 1f ceramic ca - pacitor to gnd. do not couple this pin to any other signal. tune (pin 15): vco tuning input. this frequency control pin is normally connected to the external loop filter. see the applications information section for more details. lt c6948 6948fa
12 for more information www.linear.com/LTC6948 tb (pin 16): vco bypass. this output has a 2k resistance and must be bypassed with a 2.2f ceramic capacitor to gnd. it is normally connected to cm a , cm b , and cm c with a short trace. do not couple this pin to any other signal. cm a , cm b , cm c (pins 18, 19, 20): vco bias inputs. these inputs are normally connected to tb with a short trace and bypassed with a 2.2f ceramic capacitor to gnd. do not couple these pins to any other signal. for best phase noise performance, do not place a trace between these pads underneath the package. bvco (pin 22): vco bypass pin. this output must be bypassed with a 1f ceramic capacitor to gnd. do not couple this pin to any other signal. v vco + (pin 23): 4.75v to 5.25v positive supply pin for vco circuitry. this pin should be bypassed directly to the ground plane using a 0.01f ceramic capacitor as close to the pin as possible. gnd (24): negative power supply (ground). this pin is attached directly to the die attach paddle (dap) and should be tied directly to the ground plane. v cp + (pin 25): 4v to 5.25v positive supply pin for charge pump circuitry. this pin should be bypassed directly to the ground plane using a 0.1f ceramic capacitor as close to the pin as possible. cp (pin 26): charge pump output. this bidirectional cur - rent output is normally connected to the external loop filter. see the applications information section for more details. v ref + (pin 27): 3.15v to 3.45v positive supply pin for reference input circuitry. this pin should be bypassed directly to the ground plane using a 0.1f ceramic capaci - tor as close to the pin as possible. p in func t ions lt c6948 6948fa
13 for more information www.linear.com/LTC6948 b lock diagra m rf ? 1 7 2 11 gnd 10 mute 9 29 rf + 12 v rf + 13 28 ref + ldo ldo regulator exposed pad 425mhz 100mhz 1 to 31 1 to 6, 50% 1.7v to 2.6v 32 to 1023 mute ref ? 27 v ref + r_div lock pfd o_div n_div ? b_div cal, alc control 2.24ghz to 3.74ghz (LTC6948-1) or 3.08ghz to 4.91ghz (LTC6948-2) or 3.84ghz to 5.79ghz (LTC6948-3) or 4.20ghz to 6.390ghz (LTC6948-4) 373mhz to 6.39ghz tune 15 cp v vco + gnd cm a cm b cm c gnd 1ma to 11.2ma 26 23 21 20 19 18 17 25 v cp + 24 gnd 16 tb 22 bvco 6948 bd 14 bb serial port stat cs 6 sdo sdi sclk 8 v d + 5 4 3 + ? lt c6948 6948fa
14 for more information www.linear.com/LTC6948 o pera t ion the LTC6948 is a high-performance fractional-n pll complete with a low noise vco available in four different frequency range options. the output frequency range may be further extended by utilizing the output divider (see available options table for more details). the device is able to achieve superior integrated phase noise by the combination of its extremely low in-band phase noise performance and excellent vco noise characteristics. the fractional-n feedback divider uses an advanced ? modulator, resulting in virtually no discrete modulator spurious tones. the modulator may be disabled if integer-n feedback is required. r eference i nput b uffer the pll s reference frequency is applied differentially on pins ref + and ref C . these high impedance inputs are self-biased and must be ac-coupled with 1f capacitors (see figure 1 for a simplified schematic). alternatively, the inputs may be used single-ended by applying the refer - ence frequency at ref + and bypassing ref C to gnd with a 1f capacitor. if the single-ended signal is greater than 2.7v p-p , then use a 47pf capacitor for the gnd bypass. additional options are available through serial port register h0 b to further refine the application. bits filt[1:0] control the reference input buffer s lowpass filter, and should be set based upon f ref to limit the references wideband noise. the filt [1:0] bits must be set correctly to reach the l norm normalized in-band phase noise floor. see table 1 for recommended settings. table 1. filt[1:0] programming filt[1:0] f ref 3 <20mhz 2 na 1 20mhz to 50mhz 0 >50mhz the bst bit should be set based upon the input signal level to prevent the reference input buffer from saturating. see table 2 for recommended settings and the applications information section for programming examples. table 2. bst programming bst v ref 1 <2v p-p 0 2v p-p r eference (r) d ivider a 5- bit divider, r_div , is used to reduce the frequency seen at the pfd. its divide ratio r may be set to any inte - ger from 1 to 31, inclusive. use the rd[4:0] bits found in registers h06 to directly program the r divide ratio. see the applications information section for the relationship between r and the f ref , f pfd , f vco , and f rf frequencies. p hase /f requency d etector (pfd) the phase/frequency detector (pfd), in conjunction with the charge pump, produces sour ce and sink current pulses proportional to the phase difference between the outputs of the r and n dividers. this action provides the necessary feedback to phase-lock the loop, forcing a phase align - figure 1. simplified ref interface schematic 4.2k ref + ref ? 4.2k 6948 f01 1.9v bst bias v ref + v ref + lowpass filt[1:0] 1 28 a high quality signal must be applied to the ref inputs as they provide the frequency reference to the entire pll. to achieve the part s in-band phase noise performance, apply a cw signal of at least 6dbm into 50, or a square wave of at least 0.5v p-p with slew rate of at least 40v/s. lt c6948 6948fa
15 for more information www.linear.com/LTC6948 o pera t ion figure 2. simplified pfd schematic l ock i ndicator the lock indicator uses internal signals from the pfd to measure phase coincidence between the r and n divider output signals. it is enabled by programming lkct [1:0] in the serial port register h0 c (see table 5), and produces both lock and unlock status flags, available through both the stat output and serial port register h00. the user sets the phase difference lock window time t lww for a valid lock condition with the lkwin[2:0] bits. when using the device as a fractional-n synthesizer (fractional mode), the ? modulator changes the instantaneous phase seen at the pfd on every r_div and n_div cycle. the maximum allowable time difference in this case depends upon both the vco frequency f vco and also the charge pump linearization enable bit cple (see the charge pump linearizer section for an explanation of this function). table 3 contains recommended settings for lkwin[2:0] when using the device in fractional mode. see the applications information section for examples. d q rst n div d q rst cprst up down 6948 f02 delay r div table 3. lkwin[2:0] fractional mode programming lkwin[2:0] t lww f vco (cple = 1) f vco (cple = 0) 0 5.0ns 2.97ghz 1.35ghz 1 7.35ns 2.00ghz 919mhz 2 10.7ns 1.39ghz 632mhz 3 15.8ns 941mhz 428mhz 4 23.0ns 646mhz 294mhz 5 34.5ns 431mhz 196mhz 6 50.5ns 294mhz 134mhz 7 76.0ns 196mhz 89mhz when using the device as an integer-n synthesizer (integer mode), the phase difference seen at the pfd is minimized by the feedback of the pll and no longer depends upon f vco . table 4 contains recommended settings for different f pfd frequencies. see the applications information section for examples. table 4. lkwin[2:0] integer mode programming lkwin[2:0] t lww f pfd 0 5.0ns >6.8mhz 1 7.35ns 6.8mhz 2 10.7ns 4.7mhz 3 15.8ns 3.2mhz 4 23.0ns 2.2mhz 5 34.5ns 1.5mhz 6 50.5ns 1.0mhz 7 76.0ns 660khz the pfd phase difference must be less than t lww for the counts number of successive counts before the lock indicator asserts the lock flag. the lkct[1:0] bits found in register h0c are used to set counts depending upon the application. set lkct to 0 to disable the lock indicator. see table 5 for lkct [1:0] programming and the applica - tions information section for examples. ment at the pfd s inputs. the pfd may be disabled with the cprst bit which prevents up and down pulses from being produced. see figure 2 for a simplified schematic of the pfd. lt c6948 6948fa
16 for more information www.linear.com/LTC6948 o pera t ion figure 4. simplified charge pump schematic figure 3. unlock and lock timing +t lww ?t lww unlock flag lock flag t = counts/f pfd 6948 f03 0 phase difference at pfd 26 + ? + ? cp i cp thi 0.9v v cp + v cp + tlo + ? 0.9v 6948 f04 + ? v cp + /2 cp linearizer control enable cpmid cpup up i lin cpdn cp[2:0] cpinv down nd[9:0] intn cple v cp + table 5. lkct[1:0] programming lkct[1:0] counts 0 lock indicator disabled 1 32 2 256 3 2048 when the pfd phase difference is greater than t lww , the lock indicator immediately asserts the unlock status flag and clears the lock flag, indicating an out-of-lock condition. the unlock flag is immediately de-asserted when the phase difference is less than t lww . see figure?3 for more details. note that f ref must be present for the lock and unlock flags to properly assert and clear. to the lower impedance of the loop filter components, although currents larger than 5.6ma typically cause worse spurious performance. see table 6 for programming specifics and the applications information section for loop filter examples. table 6. cp[2:0] programming cp[2:0] i cp 0 1.0ma 1 1.4ma 2 2.0ma 3 2.8ma 4 4.0ma 5 5.6ma 6 8.0ma 7 11.2ma the cpinv bit found in register h0d should be set for ap - plications requiring signal inversion from the pfd, such as for complex external loops using an inverting op amp. a passive loop filter as shown in figure 13 requires cpinv = 0. c harge p ump the charge pump, controlled by the pfd, forces sink (down) or sour ce (up) current pulses onto the cp pin, which should be connected to an appropriate loop filter. see figure 4 for a simplified schematic of the charge pump. the output current magnitude i cp may be set from 1ma to 11.2ma using the cp[2:0] bits found in serial port register h0c. a larger i cp can result in lower in-band noise due lt c6948 6948fa
17 for more information www.linear.com/LTC6948 o pera t ion charge pump functions the charge pump contains additional features to aid in system startup. see table 7 below for a summary. table 7. charge pump function bit descriptions bit description cpchi enable high voltage output clamp cpclo enable low voltage output clamp cpdn force sink current cpinv invert pfd phase cple linearizer enable cpmid enable mid-voltage bias cprst reset pfd cpup force source current cpwide extend current pulse width thi high voltage clamp flag tlo low voltage clamp flag the cpchi and cpclo bits found in register h0d enable the high and low voltage clamps, respectively. when cpchi is enabled and the cp pin voltage exceeds approximately v cp + C 0.9v , the thi status flag is set, and the charge pump sourcing current is disabled. alternately, when cpclo is enabled and the cp pin voltage is less than approximately 0.9v , the tlo status flag is set, and the charge pump sinking current is disabled. see figure?4 for a simplified schematic. the cpmid bit also found in register h0d enables a resis - tive v cp + /2 output bias which may be used to pre-bias troublesome loop filters into a valid voltage range. when using cpmid, it is recommended to also assert the cprst bit, forcing a pfd reset. both cpmid and cprst must be set to 0 for normal operation. the cpup and cpdn bits force a constant i cp source or sink current, respectively, on the cp pin. the cprst bit may also be used in conjunction with the cpup and cpdn bits, allowing a precharge of the loop to a known state, if required. cpup, cpdn, and cprst must be set to 0 to allow the loop to lock. the cpwide bit extends the charge pump output current pulse width by increasing the pfd reset paths delay value (see figure 2). cpwide is normally set to 0. charge pump linearizer when the LTC6948 is operated in fractional mode, the charge pumps current output versus its phase stimulus (its gain linearity) must be extremely accurate. the cp gain linearizer automatically adds a correction current i lin to minimize the charge pumps impact on in-band phase noise and spurious products during fractional operation. the cp gain linearizer is enabled by setting cple = 1. it is automatically disabled when in integer mode. cple should be set to 0 if cprst or cpmid are asserted to prevent the linearizer from producing unintended currents. vco the integrated vco is available in one of four frequency ranges. the output frequency range may be further ex - tended by utilizing the output divider (see available options table, for more details). the wide frequency range of the vco, coupled with the output divider capability , allows the LTC6948 to cover an extremely wide range of continuously selectable frequencies. the bb and tb pins are used to bias internal vco circuitry. the bb pin has a 2k output resistance and should be bypassed with a 1f ceramic capacitor to gnd, giving a time constant of 2ms. the tb pin has a 2.5k output resistance and should be bypassed with a 2.2f ceramic capacitor to gnd, resulting in a time constant of 5.5ms. stable bias voltages are achieved after approximately 3 time constants following power-up. vco calibration the vco must be calibrated each time its frequency is changed by changing any of f ref , the r divider value, the n divider value, or modulator fractional value, but not the o divider (see the applications information section lt c6948 6948fa
18 for more information www.linear.com/LTC6948 o pera t ion for the relationship between r, n, num, o, and the f ref , f pfd , f vco , and f rf frequencies). the output frequency is then stable over the lt c6948 s entire temperature range, regardless of the temperature at which it was calibrated, until the part is reset due to a power cycle or software power-on reset (por). the output of the b divider is used to clock digital calibra - tion circuitry as shown in the block diagram. the b value, programmed with bits bd[3:0] , and f pfd determine the calibration frequency f cal . calculate the b value using equation 1. b f pfd f cal-max (1) the maximum calibration frequency f cal-max for each part option is shown in table 8. table 8. maximum calibration frequency part f cal-max (mhz) LTC6948-1 1.0 LTC6948-2 1.33 LTC6948-3 1.7 LTC6948-4 1.8 the relationship between bits bd(3:0) and the b value is shown in table 9. table 9. bd[3:0] programming bd[3:0] b divide value 0 8 1 12 2 16 3 24 4 32 5 48 6 64 7 96 8 128 9 192 10 256 11 384 12 to 15 invalid once the rd[4:0], nd[9:0], num[17:0], and bd[3:0] bits are written and the reference frequency f ref is present and stable at the ref inputs, the vco must be calibrated by setting cal = 1 (the bit is self-clearing). the calibration cycle takes between 12 and 14 clocks of the b divider output. the mtcal bit may be set to mute the rf output during the calibration. note that the f ref frequency and tb and bb voltages must be stable for proper calibration. stable bias voltages are achieved after approximately 3 time constants following power-up. setting autocal = 1 causes the cal bit to be set auto - matically whenever any of serial port registers h06 through h0 a is written. when autocal is enabled, there is no need for a separate register write to set the cal bit. see table 10 for a summary of the vco bits. table 10. vco bit descriptions bit description autocal calibrate vco whenever registers h06 to h0a are written cal start vco calibration (auto clears) mtcal mute rf output during calibration vco automatic level control (alc) the vco uses an internal automatic level control (alc) algorithm to maintain an optimal amplitude on the vco resonator, and thus optimal phase noise performance. the user has several alc configuration and status reporting options as seen in table 11. table 11. alc bit descriptions bit description alccal auto enable alc during cal operation alcen always enable alc (overrides alccal, alcmon, and alculok) alchi alc too high flag (resonator amplitude too high) alclo alc too low flag (resonator amplitude too low) alcmon enable alc monitoring for status flags only; does not enable amplitude control alculok auto enable alc when pll unlocked lt c6948 6948fa
19 for more information www.linear.com/LTC6948 o pera t ion changes in the internal alc output can cause extremely small jumps in the vco frequency. these jumps may be acceptable in some applications but not in others. use the above table to choose when the alc is active. the alchi and alclo flags, valid only when the alc is active or the alcmon bit is set, may be used to monitor the resonator amplitude. the alc must be allowed to operate during or after a calibration cycle. at least one of the alccal, alcen, or alculok bits must be set. vco (n) d ivider the 10- bit n divider provides the feedback from the vco to the pfd. its divide ratio n is restricted to any integer from 35 to 1019, inclusive, when in fractional mode. the divide ratio may be programmed from 32 to 1023, inclusive, when in integer mode. use the nd[9:0] bits found in registers h06 and h07 to directly program the n divide ratio. see the applications information section for the relationship between n and the f ref , f pfd , f vco , and f rf frequencies. ? m odula tor the ? modulator changes the n dividers ratio each pfd cycle to achieve an average fractional divide ratio. the fractional numerator num[17:0] is programmable from 1 to 262143, or 2 18 C 1. the fractional denominator is fixed at 262144 (or 2 18 ), with the resulting fractional ratio f given by equation 4. see the applications information section for the relationship between num, f, and the f ref , f pfd , f vco , and f rf frequencies. the ? modulator uses digital signal processing (dsp) techniques to achieve an average fractional divide ratio. the modulator is clocked at the f pfd rate. this process produces output modulation noise known as quantization noise with a highpass frequency response. the external lowpass loop filter is used to filter this quantization noise to a level beneath the phase noise of the vco. this prevents the noise from contributing to the overall phase noise of the system. the loop filter must be designed to adequately filter the quantization noise. the oversampling ratio osr is defined as the ratio of the ? modulator clock frequency f pfd to the loop bandwidth bw of the pll (see equation 11). see the applications information section for guidelines concerning the osr and the loop filter. when the desired output frequency is such that the needed num value is 0, the LTC6948 should be operated in integer mode (intn = 1). in integer mode, the modulator is placed in standby, with all blocks still powered up, thus allowing it to resume fractional operation immediately. enable numerator dither mode (dithen = 1) to further reduce spurious produced by the modulator. dither has no measurable impact on in-band phase noise, and is enabled by default. see table 12 for a complete list of modulator bit descriptions. modulator reset to achieve consistent spurious performance, the modulator dsp circuitry should be re-initialized by setting rstfn? = ?1 whenever num [17:0] is changed. setting autorst = 1 causes the rstfn bit to be set automatically whenever any of serial port registers h05 through h0a are written. when autorst is enabled, there is no need for a sepa - rate register write to set the rstfn bit. see table 12 for a summary of the modulator bits. table 12. fractional modulator bit descriptions bit description autorst automatically reset modulator when registers h05 to h0a are written dithen enable fractional numerator dither intn integer mode; fractional modulator placed in standby rstfn reset modulator (auto clears) seed seed value for pseudorandom dither algorithm lt c6948 6948fa
20 for more information www.linear.com/LTC6948 o pera t ion ldo r egulator the adjustable low dropout (ldo) regulator supplies power to the modulator. the regulator requires a low esr ceramic capacitor (esr < 0.8) connected to the ldo pin (pin 7) for stability. the capacitor value may range from 0.047f to 1f. the ldo voltage is set using the ldov [1:0] bits, and should be chosen based upon the f pfd frequency to minimize power and spurious. the regulator is disabled by setting the ldoen bit to 0. when disabled by using either the ldoen or pdfn bits, the ldo pin is connected directly to v d + using a low impedance switch, and the regulator is powered down. see table 13 for programming details. table 13. ldov[1:0] and ldoen programming ldov[1:0] ldoen v ldo f pfd 0 1 1.7v 34.3mhz 1 1 2.0v 45.9mhz 2 1 2.3v 56.1mhz 3 1 2.6v 66.3mhz x 0 v d + 76.1mhz o utput (o) d ivider the 3- bit o divider can reduce the frequency from the vco to extend the output frequency range. its divide ratio o may be set to any integer from 1 to 6, inclusive, outputting a 50% duty cycle even with odd divide values. use the od[2:0] bits found in register h0b to directly program the o divide ratio. see the applications information section for the relationship between o and the f ref , f pfd , f vco , and f rf frequencies. rf o utput b uffer the low noise, differential output buffer produces a dif - ferential output power of C4.3dbm to +4.5dbm, settable with bits rfo[1:0] according to table 14. the outputs may be combined externally, or used individually. terminate any unused output with a 50 resistor to v rf + . table 14. rfo[1:0] programming rfo[1:0} p rf (differential) p rf (single-ended) 0 C4.3dbm C7.3dbm 1 C1.5dbm C4.5dbm 2 1.6dbm C1.4dbm 3 4.5dbm 1.5dbm each output is open-collector with 136 pull-up resistors to v rf + , easing impedance matching at high frequencies. see figure 5 for circuit details and the applications infor - mation section for matching guidelines. the buffer may be muted with either the omute bit, found in register h02, or by forcing the mute input low. 12 11 6948 f05 v rf + v rf + rf + 136 136 rf ? mute omute rfo[1:0] 9 mute figure 5. simplified rf interface schematic s erial p ort the sp i-compatible serial port provides control and monitoring functionality. a configurable status output stat gives additional instant monitoring. communication sequence the serial bus is comprised of cs, sclk, sdi, and sdo. data transfers to the part are accomplished by the se - rial bus master device first taking cs low to enable the lt c6948 s port. input data applied on sdi is clocked on lt c6948 6948fa
21 for more information www.linear.com/LTC6948 o pera t ion figure 6. serial port write timing diagram figure 8. serial port write sequence figure 7. serial port read timing diagram master?cs master?sclk t css t cs t ch data data 6948 f06 t ckl t ckh t css t csh master?sdi master?cs master?sclk LTC6948?sdo hi-z hi-z 6948 f07 8th clock data data t do t do t do t do the rising edge of sclk, with all transfers msb first. the communication burst is terminated by the serial bus master returning cs high. see figure 6 for details. data is read from the part during a communication burst using sdo. readback may be multidrop (more than one LTC6948 connected in parallel on the serial bus), as sdo is three-stated (hi-z) when cs = 1, or when data is not being read from the part. if the lt c6948 is not used in a multidrop configuration, or if the serial port master is not capable of setting the sdo line level between read sequences, it is recommended to attach a high value resistor of greater than 200k between sdo and gnd to ensure the line returns to a known level during hi-z states. see figure 7 for details. single byte transfers the serial port is arranged as a simple memory map, with status and control available in 15 byte-wide registers. all data bursts are comprised of at least two bytes. the seven most significant bits of the first byte are the register address, with an lsb of 1 indicating a read from the part, and lsb of 0 indicating a write to the part. the subsequent byte, or bytes, is data from/to the specified register address. see figure 8 for an example of a detailed write sequence, and figure 9 for a read sequence. figure 10 shows an example of two write communication bursts. the first byte of the first burst sent from the serial bus master on sdi contains the destination register address a6 a5 a4 a3 a2 7-bit register address hi-z master?cs master?sclk master?sdi LTC6948?sd0 a1 a0 0 d7 d6 d5 d4 d3 d2 d1 d0 8 bits of data 0 = write 6948 f08 16 clocks lt c6948 6948fa
22 for more information www.linear.com/LTC6948 o pera t ion (addr0) and an lsb of 0 indicating a write. the next byte is the data intended for the register at address addr0. cs is then taken high to terminate the transfer. the first byte of the second burst contains the destination register address (addr1) and an lsb indicating a write. the next byte on sdi is the data intended for the register at address addr1. cs is then taken high to terminate the transfer. multiple byte transfers more efficient data transfer of multiple bytes is accom - plished by using the LTC6948s register address auto- increment feature as shown in figure 11. the serial port master sends the destination register address in the first byte and its data in the second byte as before, but continues sending bytes destined for subsequent registers. byte 1s address is addr0+1, byte 2s address is addr0+2, and so on. if the register address pointer attempts to increment past 14 (h0e), it is automatically reset to 0. an example of an auto-increment read from the part is shown in figure 12. the first byte of the burst sent from the serial bus master on sdi contains the destination reg - ister address (addr0) and an lsb of 1 indicating a read. once the LTC6948 detects a read burst, it takes sdo out of the hi-z condition and sends data bytes sequentially, beginning with data from register addr0. the part ignores all other data on sdi until the end of the burst. figure 9. serial port read sequence figure 10. serial port single byte write figure 11. serial port auto-increment write figure 12. serial port auto-increment read a6 a5 a4 a3 a2 7-bit register address hi-z hi-z a1 a0 1 d7x d6 d5 d4 d3 d2 d1 d0 dx 8 bits of data 1 = read 6948 f09 master?cs master?sclk master?sdi LTC6948?sdo 16 clocks addr0 + wr hi-z master?cs master?sdi LTC6948?sdo byte 0 addr1 + wr byte 1 6948 f10 addr0 + wr hi-z master?cs master?sdi LTC6948?sdo byte 0 byte 1 byte 2 6948 f11 addr0 + rd don?t care hi-z hi-z master?cs master?sdi LTC6948?sdo 6948 f12 byte 0 byte 1 byte 2 lt c6948 6948fa
23 for more information www.linear.com/LTC6948 o pera t ion table 15. serial port register contents addr msb [6] [5] [4] [3] [2] [1] lsb r/w default h00 * * unlock alchi alclo lock thi tlo r h01 * * x[5] x[4] x[3] x[2] x[1] x[0] r/w h04 h02 pdall pdpll pdvco pdout pdfn mtcal omute por r/w h06 h03 alcen alcmon alccal alculok autocal autorst dithen intn r/w h3e h04 bd[3] bd[2] bd[1] bd[0] cple ldoen ldov[1] ldov[0] r/w h47 h05 seed[7] seed[6] seed[5] seed[4] seed[3] seed[2] seed[1] seed[0] r/w h11 h06 rd[4] rd[3] rd[2] rd[1] rd[0] * nd[9] nd[8] r/w h08 h07 nd[7] nd[6] nd[5] nd[4] nd[3] nd[2] nd[1] nd[0] r/w hfa h08 * * num[17] num[16] num[15] num[14] num[13] num[12] r/w h3f h09 num[11] num[10] num[9] num[8] num[7] num[6] num[5] num[4] r/w hff h0a num[3] num[2] num[1] num[0] * * rstfn cal r/w hf0 h0b bst filt[1] filt[0] rfo[1] rfo[0] od[2] od[1] od[0] r/w hf9 h0c lkwin[2] lkwin[1] lkwin[0] lkct[1] lkct[0] cp[2] cp[1] cp[0] r/w h4f h0d cpchi cpclo cpmid cpinv cpwide cprst cpup cpdn r/w he4 h0e rev[3] rev[2] rev[ 1] rev [0] pa rt [3] part [2] part [1] part [0] r hxx? *unused ? varies depending on version multidrop configuration several LTC6948 s may share the serial bus. in this mul - tidrop configuration, sclk, sdi, and sdo are common b etw een all parts. the serial bus master must use a separate cs for each LTC6948 and ensure that only one device has cs asserted at any time. it is recommended to attach a high value resistor to sdo to ensure the line returns to a known level during hi-z states. serial port registers the memory map of the LTC6948 may be found below in table 15, with detailed bit descriptions found in table 16. the register address shown in hexadecimal format under the addr column is used to specify each register. each register is denoted as either read-only (r) or read-write (r/w). the register s default value on device power-up or after a reset is shown at the right. the read-only register at address h00 is used to determine different status flags. these flags may be instantly output on the stat pin by configuring register h01 . see stat output section that follows for more information. the read-only register at address h0 e is a rom byte for device identification. stat output the stat output pin is configured with the x [5:0] bits of register h01. these bits are used to bit-wise mask, or enable, the corresponding status flags of status register h00, according to equation 2. the result of this bit-wise boolean operation is then output on the stat pin. s tat = or (reg00[5:0] and reg01[5:0]) (2) or , expanded, s tat = (unlock and x[5]) or (alchi and x[4]) or (alclo and x[3]) or (lock and x[2]) or (thi and x[1]) or (tlo and x[0]) for example, if the application requires st at to go high whenever the alchi, alclo, or thi flags are set, then x[4], x[3], and x[1] should be set to 1, giving a register value of h1a. lt c6948 6948fa
24 for more information www.linear.com/LTC6948 block power-down control the LTC6948 s power-down control bits are located in register h02 , described in table 16. different portions of the device may be powered down independently. care must be taken with the lsb of the register, the por (power-on- reset) bit. when written to a 1, this bit forces a full reset of the part s digital circuitry to its power-up default state. o pera t ion table 16. serial port register bit field summary bits description default alccal auto enable alc during cal operation 1 alcen always enable alc (override) 1 alchi alc too hi flag alclo alc too low flag alcmon enable alc monitor for status flags only 0 alculok enable alc when pll unlocked 1 autocal calibrate vcos whenever registers h06 to h0a are written 1 autorst reset modulator whenever registers h05 to h0a are written 1 bd[3:0] calibration b divider value h4 bst ref buffer boost current 1 cal start vco calibration (auto clears) 0 cp[2:0] cp output current h7 cpchi enable hi-voltage cp output clamp 1 cpclo enable low-voltage cp output clamp 1 cpdn force cp pump down 0 cpinv invert cp phase 0 cple cp linearizer enable 0 cpmid cp bias to mid-rail 1 cprst cp tri-state 1 cpup force cp pump up 0 cpwide extend cp pulse width 0 dithen enable fractional numerator dither 1 filt[1:0] ref input buffer filter h3 intn integer mode; fractional modulator placed in standby 0 bits description default ldoen ldo enable 1 ldov[1:0] ldo voltage h3 lkct[1:0] pll lock cycle count h1 lkwin[2:0] pll lock indicator window h2 lock pll lock indicator flag mtcal mute rf output during calibration 1 nd[9:0] n divider value (nd[9:0] 32) h0fa num[17:0] fractional numerator value h3fff od[2:0] output divider value (0 < od[2:0] < 7) h1 omute mutes rf output 1 part [3:0] part code (h01 for -1, h02 for -2, h03 for -3, h04 for -4 version) h01, h02, h03, h04 pdall full chip powerdown 0 pdfn powers down ldo and modulator clock 0 pdout powers down o_div, rf output buffer 0 pdpll powers down ref, r_div, pfd, cpump, n_div 0 pdvco powers down vco, n_div 0 por force power-on-reset 0 rd[4:0] r divider value (rd[4:0] > 0) h001 rev[3:0] rev code h1 rfo[1:0] rf output power h3 rstfn force modulator reset (auto clears) 0 seed[7:0] modulator dither seed value h11 thi cp clamp high flag tlo cp clamp low flag unlok pll unlock flag x[5:0] stat output or mask h04 lt c6948 6948fa
25 for more information www.linear.com/LTC6948 a pplica t ions i n f or m a t ion i ntroduction a pll is a complex feedback system that may conceptually be considered a frequency multiplier. the system multiplies the frequency input at ref and outputs a higher frequency at rf . the pfd, charge pump, n divider, vco and external loop filter form a feedback loop to accurately control the output frequency (see figure 13). the external loop filter is used to set the plls loop bandwidth bw. lower bandwidths generally have better spurious performance and lower modulator quantization noise. higher bandwidths can have better total integrated phase noise. the r and o divider and input frequency f ref are used to set the output frequency resolution. when in fractional mode, the ? modulator changes the n dividers ratio each pfd cycle to produce an average fractional divide ratio. this achieves a much smaller frequency resolution for a given f pfd as compared to integer mode. o utput f requency when the loop is locked, the frequency f vco (in hz) produced at the output of the vco is determined by the reference frequency f ref , the r and n divider values, and the fractional value f, given by equation 3: f vco = f ref ? n + f ( ) r (3) where the fractional value f is given by equation 4: f = num 2 18 (4) num is programmable from 1 to 262143, or 2 18 C 1. when using the LTC6948 in integer mode, f = 0. the pfd frequency f pfd is given by the following equation: f pfd = f ref r (5) and f vco may be alternatively expressed as: f vco = f pfd ? (n + f) (6) the output frequency f rf produced at the output of the o divider is given by equation 7: f rf = f vco o (7) using the above equations, the minimum output frequency resolution f step(min) produced by a unit change in the fractional numerator num while in fractional mode is given by equation 8: f step(min) = f ref r ? o ? 2 18 (8) figure 13. pll loop diagram r_div n_div r o_div o (n + f) f pfd LTC6948 ref (f ref ) f vco k pfd k vco 26 rf (f rf ) 15 cp loop filter (fourth order) lf(s) 6948 f13 tune i cp ? r z c i c p c2 lf(s) r1 l1 lt c6948 6948fa
26 for more information www.linear.com/LTC6948 a pplica t ions i n f or m a t ion alternatively, to calculate the numerator step size num step needed to produce a given frequency step f step(frac) , use equation 9: num step = f step(frac) ? r ? o ? 2 18 f ref (9) the output frequency resolution f step(int) produced by a unit change in n while in integer mode is given by equa - tion 10: f step(int) = f ref r ? o (10) l oop f il ter d esign a stable pll system requires care in designing the external loop filter . the linear technology fracnwizard application, available from www.linear.com, aids in design and simula - tion of the complete system. the loop design should use the following algorithm : 1) determine the output frequency f rf and frequency step size f step based on application requirements. using equations 3, 5, 7, and 8, change f ref , n, r, and o until the application frequency constraints are met. use the minimum r value that still satisfies the constraints. then calculate b using equation 1 and tables 8 and 9. 2) select the open loop bandwidth bw constrained by f pfd and oversampling ratio osr. the osr is the ratio of f pfd to bw (see equation 11): osr = f pfd bw or b w = f pfd osr (11) where bw and f pfd are in hz. a stable loop, both in integer and fractional mode, requires that the osr is greater than or equal to 10. further, in fractional mode, osr must be high enough to allow the loop filter to reduce modulator quantiza - tion noise to an acceptable level. choosing a higher order loop filter when using the ? modulator allows for a smaller osr, and thus a larger loop bandwidth. linear t echnologys fracnwizard helps choose the appropriate osr and bw values. 3) select loop filter component r z and charge pump cur - rent i cp based on bw and the vco gain factor, k vco . bw (in hz) is approximated by the following equation: bw ? i cp ? r z ? k vco 2 ? ? n or r z = 2 ? ? bw ? n i cp ? k vco (12) where k vco is in hz/v, i cp is in amps, and r z is in ohms. k vco is obtained from the vco tuning sensitivity in the electrical characteristics. use i cp = 5.6ma to lower in-band noise unless component values force a lower setting. 4) select loop filter components c i and c p based on bw and r z . a reliable second-order loop filter design can be achieved by using the following equations for the loop capacitors (in farads). c i = 3.5 2 ? ? bw ? r z (13) c p = 1 7 ? ? bw ? r z (14) use fracnwizard to aid in the design of higher order loop filters. lt c6948 6948fa
27 for more information www.linear.com/LTC6948 d esign and p rogramming e xample this programming example uses the dc1959 with the LTC6948-2. assume the following parameters of interest: f ref = 100mhz at 7dbm into 50 f step = 50khz f rf = 1921.650mhz from the electrical characteristics table: f vco = 3.080ghz to 4.910ghz k vco% = 4.7%hz/v to 7%hz/v determining divider values following the loop filter design algorithm, first determine all the divider values. the maximum f pfd while in fractional mode is less than 100mhz, so r must be greater than 1. r = 2 then, using equations 5 and 7, calculate the following values: o = 2 f pfd = 50mhz then using equation 6: n + f = 2 ? 1921.650mhz 50mhz = 76.866 therefore: n = 76 f = 0.866 then, from equation 4, num = 0.866 ? 2 18 = 227017 also, from equation 1 and tables 8 and 9 determine b: b = 48 and bd[3:0] = h5 a calibration cycle takes 12 to 14 clock cycles of f cal . this gives a vco calibration time of approximately: t cal ? 14 f cal = 14 ? b f pfd = 13.4s selecting filter type and loop bandwidth the next step in the algorithm is choosing the open loop bandwidth. select the minimum bandwidth resulting from the below constraints. 1) the osr must be at least 10 (sets absolute maximum bw). 2) the integrated phase noise due to thermal noise should be minimized, neglecting any modulator noise. 3) the loop bandwidth must be narrow enough to ad - equately filter the modulators quantization noise. fracnwizard reports the loop bandwidths resulting from each of the above constraints. the quantization noise con - strained results vary according to the shape of the external loop filter. fracnwizard reports an optimal bandwidth for several filter types. fracnwizard reports the thermal noise optimized loop bandwidth is 211khz. filter 3 (fourth order response) has a quantization noise constrained bw of 150khz, making it a good choice. select filter 3 and use the smaller of the two bandwidths (150khz) for optimal integrated phase noise. use equation 11 to calculate osr: osr = 50mhz 150khz = 333.3 a pplica t ions i n f or m a t ion lt c6948 6948fa
28 for more information www.linear.com/LTC6948 a pplica t ions i n f or m a t ion loop filter component selection now set loop filter resistor r z and charge pump current i cp . because the k vco varies over the vcos frequency range, using the k vco geometric mean gives good results: k vco = 3.843 ? 10 9 ? 0.047 ? 0.07 = 220.4mhz / v using an i cp of 5.6ma , the fracnwizard uses equation?12 to determine r z : r z = 2 ? ? 150k ? 76 5.6m ? 220.4m r z = 58.0 for the 4th order filter 3, fracnwizard uses modified equations 13 and 14 to calculate c i , c p : c i = 4.5 2 ? ? 150k ? 58 = 82.3nf c p = 1 10.5 ? ? 150k ? 58 = 3.5nf fracnwizard calculates r1, l1, and c2 to be: r1 = 58.0 c2 = 2.3nf l1 = 7.8h status output programming this example will use the st at pin to alert the system whenever the LTC6948 generates a fault condition. pro - gram x[5], x[4], x[3], x[1], x [0] = 1 to for ce the stat pin high whenever any of the unlock, alchi, alclo, thi, or tlo flags asserts: re g01 = h3b power register programming for correct pll operation all internal blocks should be enabled. omute may remain asserted (or the mute pin held low) until programming is complete. for omute = 1: re g02 = h02 vco alc, autocal, and autorst programming set the alc options (alcmon = alculok = alccal? =?1), the auto reset options (autocal = autorst = 1), and the ? modulator modes (dithen = 1, intn = 0) at the same time: re g03 = h7e the alc will only be active during a calibration cycle or when the loop is unlocked, but the alchi and alclo status conditions will be monitored continuously. the vco will be calibrated and the ? modulator will be reset at the end of the spi write communication burst (assuming an auto-increment write is used to write all registers). ldo programming use table 13 and f pfd = 50mhz to determine v(ldo) and ldov[1:0]: v(ldo) = 2.3v and ldov[1:0] = 2 use ldov [1:0], ldoen = 1 to enable the ldo, and the previously determined bd[3:0] value to set reg04. cple should be set to 1 to reduce in-band noise and spurious due to the ? modulator: re g04 = h5e seed programming the seed[7:0] value is used to initialize the ? modulator dither circuitry. use the default value: re g05 = h11 lt c6948 6948fa
29 for more information www.linear.com/LTC6948 a pplica t ions i n f or m a t ion r and n divider and numerator programming program registers reg06 to reg0a with the previously determined r and n divider and numerator values. because the autorst and autocal bits were previously set to 1, cal and rstfn do not need to be set: re g06 = h10 re g07 = h4c re g08 = h37 re g09 = h6c re g0a = h90 reference input settings and output divider programming from table 1, filt = 0 for a 100mhz reference frequency. next, convert 7dbm into v pCp . for a cw tone, use the following equation with r = 50: v p-p ? r ? 10 (dbm C 21)/20 (15) this gives v p-p = 1.41v , and, according to table 2, set bst = 1. now program reg0b, assuming maximum rf output power (rfo [1:0] = 3 according to table 14) and od [2:0] = 2 : re g0b = h9a lock detect and charge pump current programming next, determine the lock indicator window from f pfd . from table 3 we see that lkwin [1:0] = 0 with a t lww of 5ns for cple = 1 and f vco = 3.843ghz . the LTC6948 will consider the loop locked as long as the phase coincidence at the pfd is within 90, as calculated below. phase = 360 ? t lww ? f pfd = 360 ? 5n ? 50m = 90 choosing the correct counts value depends upon the o sr. smaller ratios dictate larger counts values, although application requirements will vary. a counts value of 32 will work for the osr of 333. from table 5, lkct [1:0]?= ?1 for 32 counts. using table 6 with the previously selected i cp of 5.6ma gives cp [3:0] = 7. this gives enough information to pro - gram reg0c: re g0c = h0d charge pump function programming this example uses the additional voltage clamp features to allow the monitoring of fault conditions by setting cpchi?= ?1 and cpclo = 1. if something occurs and the system can no longer lock to its intended frequency, the charge pump output will move toward either gnd or v cp + , thereby setting either the tlo or thi status flags, respectively. disable all the other charge pump functions (cpmid, cpinv, cprst, cpup, and cpdn), allowing the loop to lock: re g0d = hc0 the loop should now lock. now un-mute the output by setting omute = 0 (assumes the mute pin is high). re g02 = h04 lt c6948 6948fa
30 for more information www.linear.com/LTC6948 a pplica t ions i n f or m a t ion r eference s ource c onsiderations a high quality signal must be applied to the ref inputs as they provide the frequency reference to the entire pll. as mentioned previously, to achieve the part s in-band phase noise performance, apply a cw signal of at least 6dbm into 50 , or a square wave of at least 0.5v p-p with slew rate of at least 40v/s. the LTC6948 may be driven single-ended to cmos levels (greater than 2.7v p-p ). apply the reference signal at ref + , and bypass ref C to gnd with a 47pf capacitor. the bst bit must also be set to 0, according to guidelines given in table 2. the LTC6948 achieves an integer mode in-band normalized phase noise floor l norm(int) = C226dbc /hz typical, and a fractional mode phase noise floor l norm(frac) = C225 dbc/hz typical. to calculate its equivalent input phase noise floor l in , use the following equation 16. l in = l norm + 10 ? log 10 (f ref ) (16) for examp le, using a 10mhz reference frequency in integer mode gives an input phase noise floor of C156dbc/hz. the reference frequency source s phase noise must be at least 3db better than this to prevent limiting the overall system performance. i n -b and o utput p hase n oise the in-band phase noise floor l out produced at f rf may be calculated by using equation 17. l out = l norm + 10 ? log 10 (f pfd ) (17) + 20 ? log 10 (f rf /f pfd ) or l out l norm + 10 ? log 10 (f pfd ) + 20 ? log 10 (n/o) where l norm is C 226dbc /hz for integer mode and C225dbc /hz for fractional mode. see the typical perfor - mance characteristics section for graphs showing l norm variation versus i cp and f vco . as can be seen from equation 17 for a given pfd frequency f pfd , the output in-band phase noise increases at a 20db- per-decade rate with the n divider count. so, for a given output frequency f rf , f pfd should be as large as possible (or n should be as small as possible) while still satisfying the applications frequency step size requirements. o utput p hase n oise d ue to 1/f n oise in-band phase noise at very low offset frequencies may be influenced by the LTC6948s 1/f noise, depending upon f pfd . use the normalized in-band 1/f noise l 1/f of C274dbc/ hz with equation 18 to approximate the output 1/f phase noise at a given frequency offset f offset . l out(1/f) (f offset ) = l 1/f + 20 ? log 10 (f rf ) (18) C 10 ? log 10 (f offset ) unlike the in-band noise floor l out , the 1/f noise l out(1/f) does not change with f pfd , and is not constant over offset frequency. see figure 14 for an example of integer mode in-band phase noise for f pfd equal to 3mhz and 100mhz. the total phase noise will be the summation of l out and l out(1/f) . figure 14. theoretical integer mode in-band phase noise, f rf = 2500mhz offset frequency (hz) 10 phase noise (dbc/hz) ?110 ?100 100k 6948 f14 ?120 ?130 100 1k 10k ?90 total noise f pfd = 3mhz total noise f pfd = 100mhz 1/f noise contribution lt c6948 6948fa
31 for more information www.linear.com/LTC6948 ib spur level (dbc) ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 6948 f15 frequency offset from 3ghz (hz) 1k 10k 10m 1m 100k f vco 3ghz f pfd = 50mhz loop bw = 130khz cple = 1 n = 60 swept num figure 15. integer boundary spur power vs frequency offset from boundary, LTC6948-1 i nteger b oundary s purs integer boundary spurs are caused by intermodulation between harmonics of the pfd frequency f pfd and the vco frequency f vco . the coupling between the frequency source harmonics can occur either on- or off-chip. the spurs are located at offset frequencies defined by the beat frequency between the reference harmonics and the vco frequency, and are attenuated by the loop filter. the spurs only occur while in fractional mode. integer boundary spurs are most commonly seen when the fractional value f approaches either zero or one such that the vco frequency offset from an integer frequency is within the loop bandwidth: f pfd ? f bw or f pfd ? (1 C f) bw the spur will have a relatively constant power in-band, and be attenuated by the loop out-of-band. an example integer boundary spur measurement is shown in figure 15. rf o utput m a tching the rf outputs may be used in either single-ended or dif - ferential configurations. using both rf outputs differentially will result in approximately 3db more output power than single-ended. impedance matching to an external load in both cases requires external chokes tied to v rf + . measured rf s-parameters are shown below in table?17 to aid in the design of impedance matching networks. table 17. single-ended rf output impedance frequency (mhz) impedance () s11 (db) 100 133.0 C j16.8 C6.7 500 110.8 C j46.1 C6.8 1000 74.9 C j57.0 C6.9 1500 49.0 C j51.3 C6.7 2000 34.4 C j41.4 C6.5 2500 27.0 C j32.1 C6.5 3000 23.2 C j24.1 C6.6 3500 21.6 C j15.9 C7.1 4000 20.9 C j7.7 C7.5 4500 20.1 C j0.2 C7.4 5000 18.1 + j7.4 C6.4 5500 16.7 + j12.5 C5.6 6000 17.1 + j16.1 C5.5 6500 20.2 + j20.1 C6.2 7000 26.9 + j24.6 C7.6 7500 38.8 + j32.3 C8.8 8000 52.9 + j43.1 C8.2 a pplica t ions i n f or m a t ion lt c6948 6948fa
32 for more information www.linear.com/LTC6948 a pplica t ions i n f or m a t ion single-ended impedance matching is accomplished using the circuit of figure 16, with component values found in table 18. using smaller inductances than recommended can cause phase noise degradation, especially at lower center frequencies. table 18. suggested single-ended matching component values f rf (mhz) l c (nh) c s (pf) 350 to 1500 180 270 1000 to 5800 68 100 return loss measured on the dc1959 using the above component values is shown in figure 17. a broadband match is achieved using an {l c , c s } of either {68nh, 100pf} or {180nh, 270pf} . however, for maximum output power and best phase noise performance, use the recommended component values of table 18. l c should be a wirewound inductor selected for maximum q factor and srf, such as the coilcraft hp series of chip inductors. the LTC6948 s differential rf outputs may be combined using an external balun to drive a single-ended load. the advantages are approximately 3db more output power than each output individually and better 2nd order harmonic performance. for lower frequencies, transmission line (tl) baluns such as the m/a-com mabact0065 and the toko #617db-1673 provide good results. at higher frequencies, surface mount (smt) baluns such as those produced by tdk, anaren, and johanson technology, can be attractive alternatives. see table 19 for recommended balun part numbers versus frequency range. the listed smt baluns contain internal chokes to bias rf and also provide input-to-output dc isolation. the pin denoted as gnd or dc feed should be connected to the v rf + voltage. figure 18 shows a surface mount balun s connections with a dc feed pin. table 19. suggested baluns f rf (mhz) part number manufacturer type 350 to 900 #617db-1673 toko tl 400 to 600 hhm1589b1 tdk smt 600 to 1400 bd0810j50200 anaren smt 600 to 3000 mabact0065 m/a-com tl 1000 to 2000 hhm1518a3 tdk smt 1400 to 2000 hhm1541e1 tdk smt 1900 to 2300 2450bl15b100e johanson smt 2000 to 2700 hhm1526 tdk smt 3700 to 5100 hhm1583b1 tdk smt 4000 to 6000 hhm1570b1 tdk smt the listed tl baluns do not provide input-to-output dc isolation and must be ac-coupled at the output. figure 19 displays rf connections using these baluns. figure 17. rf single-ended return loss 0 1 2 3 4 5 6 7 frequency (ghz) s11 (db) ?6 ?4 ?2 6947 f17 ?10 ?16 0 ?8 ?12 ?14 68nh, 100pf 180nh, 270pf figure 16. single-ended output matching schematic rf +(?) l c c s 50 to 50 load v rf + rf ?(+) l c c s 6948 f16 v rf + lt c6948 6948fa
33 for more information www.linear.com/LTC6948 figure 20. example exposed pad land pattern 6948 f20 a pplica t ions i n f or m a t ion figure 18. example smt balun connection figure 19. example tl balun connection LTC6948 v rf + rf ? rf + to 50 load 6948 f18 12 balun 2 3 1 5 4 6 11 balun pin configuration 1 2 3 4 5 6 unbalanced port gnd or dc feed balanced port balanced port gnd nc LTC6948 v rf + rf ? rf + to 50 load pri sec 6948 f19 12 11 s upply b ypassing and pcb l ayout g uidelines care must be taken when creating a pcb layout to mini - mize power supply decoupling and ground inductances. all power supply v + pins should be bypassed directly to the ground plane using a 0.1f ceramic capacitor as close to the pin as possible. multiple vias to the ground plane should be used for all ground connections, including to the power supply decoupling capacitors. the packages exposed pad is a ground connection, and must be soldered directly to the pcb land pattern. the pcb land pattern should have multiple thermal vias to the ground plane for both low ground inductance and also low thermal resistance (see figure 20 for an example). see qfn package users guide , page 8, on linear technology websites packaging information page for specific recom - mendations concerning land patterns and land via solder masks. a link is provided below. http ://www.linear.com/designtools/packaging lt c6948 6948fa
34 for more information www.linear.com/LTC6948 r eference s ignal r outing , s purious , and p hase n oise the charge pump operates at the pfd s comparison frequency f pfd . the resultant output spurious energy is small and is further reduced by the loop filter before it modulates the vco frequency. however, improper pcb layout can degrade the LTC6948s inherent spurious performance. care must be taken to prevent the reference signal f ref from coupling onto the vcos tune line, or into other loop filter signals. example suggestions are the following. a pplica t ions i n f or m a t ion 1) do not share power supply decoupling capacitors between same-voltage power supply pins. 2) use separate ground vias for each power supply decoupling capacitor, especially those connected to v ref + , v d + , ldo, v cp + , and v vco + . 3) physically separate the reference frequency signal from the loop filter and vco. 4) do not place a trace between the cm a , cm b , and cm c pads underneath the package, as worse phase noise could result. lt c6948 6948fa
35 for more information www.linear.com/LTC6948 output power (dbm) ?20 noise floor (dbm/hz) ?148 ?150 ?152 ?156 ?160 ?154 ?158 ?162 ?15 0 6948 ta02c 5 ?5 ?10 f lo = 2100mhz baseband = 2khz sine output frequency (mhz) 1500 (dbc) ?20 ?30 ?40 ?50 ?60 ?70 ?80 1700 1900 2300 2100 6948 ta02b 2500 baseband = 100khz at 500mv pk lo leakage ratio unadjusted image rejection typical a pplica t ions driving a modulator lo for high image rejection and low noise floor measured image rejection and lo leakage ratio vs output frequency measured noise floor at 70mhz offset vs rf output power unused output available for other use 50 0.1f r = 1, f pfd = 61.44mhz n = 73.24 to 84.64 lbw = 180khz o = 2 1f 0.01f 5v 3.3v 0.1f 68nh 68nh 0.01f 3.3v 66.5 100pf 100pf 1.8nf 3.3v LTC6948-3 stat tune cs mute sdi v d + ldo rf + rf ? gnd sclk tb gnd v rf + ref + bb sdo cm c cm b cm a gnd bvco v vco + gnd v cp + cp v ref + ref ? gnd 0.1f 61.44mhz 51.1 1f 3.3v 1f 0.1f 3.3v 1f 2.2f 15 spi bus 10h 66.5 68nf 2.2nf avago vmmk-2503 4.7f mini-circuits lfcn-2600+ lpf 50 1 1nf 6.8pf 1nf 5v 3.3v ltc5588-1 baseband i-channel baseband q-channel en gnd lop lom gnd nc linopt gnd bbmq bbpq gnd gndrf gnd gndrf v cc1 gnd bbmi bbpi gnd gndrf v cc2 gndrf gndrf nc nc rf 100nf 6948 ta02a f lo = 1500mhz to 2600mhz in 117.2hz steps rf output, 1500mhz to 2600mhz carrier p lo = 13.5dbm, ~ 36 for more information www.linear.com/LTC6948 p ackage descrip t ion please refer to http://www.linear.com/product/LTC6948#packaging for the most recent package drawings. ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev c) 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wghd-3). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0816 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05 ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev c) lt c6948 6948fa
37 for more information www.linear.com/LTC6948 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 04/17 corrected defaults for alculok and bd[3:0]. 24 lt c6948 6948fa
38 for more information www.linear.com/LTC6948 ? linear technology corporation 2014 lt 0417 rev a ? printed in usa www.linear.com/LTC6948 part number description comments ltc6946-x ultralow noise and spurious integer-n synthesizer with integrated vco 370mhz to 6.4ghz, C226dbc/hz normalized in-band phase noise floor, C157dbc/hz wideband output phase noise floor ltc6945 ultralow noise and spurious integer-n synthesizer 350mhz to 6ghz, C226dbc/hz normalized in-band phase noise floor, C157dbc/hz wideband output phase noise floor ltc6947 ultralow noise and spurious fractional-n synthesizer 350mhz to 6ghz, C226dbc/hz normalized in-band phase noise floor, C157dbc/hz wideband output phase noise floor ltc6957 low phase noise, dual output buffer/driver/ logic converter optimized conversion of sine waves to logic levels, lvpecl/lvds/cmos outputs, dc-300mhz, 45fsrms additive jitter (lvpecl) ltc5540/ltc5541/ ltc5542/ltc5543 high dynamic range downconverting mixers 8db conversion gain, 26.4dbm iip3, 9.6db nf, 600mhz to 4ghz ltc5590/ltc5591/ ltc5592/ltc5593 high linearity dual mixers 600mhz to 4.5ghz, 8.5db gain, 26.2dbm iip3, 9.9db nf ltc5569 broadband dual mixer 300mhz to 4ghz, 26.8dbm iip3, 2db gain, 11.7db nf, 600mw power ltc5588-1 ultrahigh oip3 i/q modulator 200mhz to 6ghz, 31dbm oip3, C160.6dbm/hz noise floor lt ? 5575 direct conversion i/q demodulator 800mhz to 2.7ghz, 22.6dbm iip3, 60dbm iip2, 12.7db nf r ela t e d p ar t s typical a pplica t ions unused output available for other use 50 0.1f r = 5, f pfd = 63.1mhz n = 66.6 to 95.1 lbw = 218khz o = 1 1f 0.01f 5v 3.3v 0.1f 68nh 68nh 0.01f 3.3v 71.5 100pf 100pf 1.5nf 3.3v f lo = 8400mhz to 12000mhz in 481.4hz steps p lo = 14dbm to 16dbm LTC6948-4 stat tune cs mute sdi v d + ldo rf + rf ? gnd sclk tb gnd v rf + ref + bb sdo cm c cm b cm a gnd bvco v vco + gnd v cp + cp v ref + ref ? gnd 0.1f 315.5mhz, 15dbm 315.5mhz data- converter clock crystek ccso-914x 51.1 1f 3.3v 1f 0.1f 3.3v 1f 2.2f 16.5 16.5 15 16.5 6948 ta03a spi bus 10h 71.5 47nf 4.7nf 2.2nf ma-com xx1002-qh x2 5v 1f 1nf 0.01f 1f generating a 12ghz lo signal system phase noise f rf = 12.024ghz offset frequency (hz) ?130 ?140 phase noise (dbc/hz) ?110 ?80 ?90 ?120 ?100 1k 100k 1m 10m 100m 6948 ta03b ?150 10k rms noise = 0.825 rms jitter = 191fs f pfd = 63.1mhz loop bw = 218khz intn = 0 lt c6948 6948fa

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